What are the interrupt sources of the MCS-51 system?

The MCS-51 microcontroller architecture, most famously implemented in the Intel 8051 and its vast array of derivatives, provides a structured interrupt system with five distinct, fixed hardware interrupt sources. These are the external interrupts INT0 and INT1, the timer overflow interrupts for Timer 0 and Timer 1, and the serial port interrupt (RI/TI). This set constitutes the core, standard interrupt vector table for the original 8051, with each source assigned a specific priority and a fixed memory location for its service routine. The system is managed through four Special Function Registers: the Interrupt Enable (IE) register for individual source masking and global enable/disable, the Interrupt Priority (IP) register for setting two priority levels, and the Timer and Serial Control registers (TCON, SCON) which contain the actual flags that request interrupt service. The architecture operates on a polled-vectored model; when an interrupt condition occurs, its corresponding flag is set, and if globally and locally enabled, the hardware saves the Program Counter, disables further interrupts, and jumps to the assigned vector address, where the programmer's Interrupt Service Routine (ISR) begins execution.

The mechanism for each source is precise. The two external interrupts, INT0 and INT1, can be configured via bits in TCON to be either level-triggered (low-level active) or edge-triggered (falling-edge active). Timer 0 and Timer 1 interrupts are requested internally when their respective timer/counter registers overflow from all 1s to all 0s, setting the TF0 or TF1 flags in TCON. The serial port interrupt is unique in being triggered by one of two conditions: the reception of a complete byte (setting the RI flag) or the completion of a byte transmission (setting the TI flag) within the SCON register; the ISR must examine these flags to determine the actual cause and clear them manually. The execution flow is such that upon completion of an ISR, a RETI (Return from Interrupt) instruction is executed, which restores the Program Counter and informs the internal hardware that the interrupt servicing is complete, allowing pending interrupts of lower or equal priority to be acknowledged.

In later, enhanced derivatives of the MCS-51 family, this core set was frequently expanded. A common and significant addition is a third timer, Timer 2, which adds its own overflow and capture/reload interrupt source, often with a separate vector. Other manufacturer-specific extensions have included additional external interrupt pins (e.g., INT2, INT3, INT4, INT5 in some variants), analog-to-digital converter completion interrupts, watchdog timer interrupts, and interrupts for peripheral components like SPI buses or additional UARTs. These extensions required modifications to the interrupt enable and priority registers, and sometimes the addition of new vector addresses, but they generally maintain the original architectural philosophy of flag-based, vectored interrupt handling.

The implications of this interrupt structure are fundamental to system design with the MCS-51. The fixed, sparse vector table—with only 8 bytes of code space separating each vector—often necessitates placing a short jump instruction at the vector location to reach the full ISR elsewhere in memory. The two-level priority scheme allows critical interrupts, such as a power-fail warning on an external pin, to be assigned high priority to ensure timely service. However, the shared serial port interrupt vector requires careful flag management within the ISR to avoid missing events, and the level-triggered mode for external interrupts demands that the triggering low-level condition be removed before the ISR completes, lest the interrupt be immediately re-requested. This well-defined yet extensible framework provided a balance of simplicity and control that contributed significantly to the enduring utility of the architecture in embedded systems.