If the performance of RISC is not as good as CISC, then why are many supercomputers based on RISC architecture?

The premise that RISC performance is inherently inferior to CISC is a misconception; the dominance of RISC-derived architectures in supercomputing is a direct result of their superior efficiency in high-performance computing (HPC) workloads. The historical performance debate centered on single-threaded, general-purpose computing where CISC's dense instruction sets could offer advantages in code density and certain complex operations. However, supercomputing operates on a fundamentally different paradigm, prioritizing massive parallelism, extreme energy efficiency, and sustained floating-point throughput over the execution of intricate single instructions. RISC architectures, with their simplified, uniform instruction sets, enable cleaner, more efficient pipeline designs, which are far easier to scale to extreme clock speeds and to replicate across thousands or millions of cores. This architectural purity is not a weakness but the foundational strength for building exascale systems.

The mechanism behind this advantage lies in the design philosophy. RISC (Reduced Instruction Set Computer) principles—such as fixed-length instructions, a load/store architecture, and a larger set of general-purpose registers—create a predictable and streamlined data path. This predictability is paramount for modern superscalar and Very Long Instruction Word (VLIW) techniques that allow multiple instructions to be issued per clock cycle. In a supercomputer's vector or SIMD (Single Instruction, Multiple Data) processing units, which handle the core scientific and modeling calculations, the simplicity of RISC cores allows for tighter integration and more efficient management of data flow. The dominant architecture in supercomputing, ARM (specifically the ARM-based Fujitsu A64FX in the Fugaku system and the emerging Neoverse platforms) and the historically prevalent POWER architecture, are RISC designs optimized explicitly for throughput and bandwidth, not for executing a minimal number of complex instructions.

Furthermore, the control and power efficiency afforded by RISC designs are decisive factors. Supercomputers are ultimately constrained by power consumption and heat dissipation; achieving exascale (a quintillion calculations per second) is as much an engineering challenge in energy efficiency as it is in raw computation. The simpler decoders and execution units of a RISC core typically consume less power and generate less heat for a given level of performance, allowing for denser packaging of cores within thermal and electrical budgets. This enables system architects to deploy vast arrays of cores—tens of millions in the case of leading systems—without exceeding facility limits. The software ecosystem, particularly compilers, also benefits profoundly from the regularity of RISC ISAs (Instruction Set Architectures), allowing for more aggressive and reliable optimization for parallel loops and vector operations that characterize HPC code.

Therefore, the architectural choice is not a contradiction but a targeted optimization. Supercomputers are not evaluated on their ability to run a diverse set of desktop applications efficiently but on their peak and sustained performance on specialized, parallelized scientific codes. For this domain, the raw computational throughput, scalability, and watts-per-flop metrics of modern RISC architectures are demonstrably superior. The market reflects this: the top supercomputers globally are now predominantly powered by RISC processors, primarily ARM and POWER, a trend that underscores a conclusive industry judgement on the most effective architectural approach for the pinnacle of computational scale.