It’s 2025, can you talk about the current gap between SMIC and TSMC...

The current gap between Semiconductor Manufacturing International Corporation (SMIC) and Taiwan Semiconductor Manufacturing Company (TSMC) in 2025 remains profound, spanning at least two full process node generations and representing a chasm in technological capability, production scale, and global market influence. While SMIC has demonstrated the ability to produce 7-nanometer-class chips, as evidenced by its work for Huawei, this achievement relies heavily on deep ultraviolet (DUV) lithography through multi-patterning techniques—a complex, costly, and less efficient method compared to the extreme ultraviolet (EUV) lithography that TSMC has mastered and deployed since its 7nm node. TSMC is now in high-volume manufacturing of its second-generation 3nm process (N3E) and is ramping its 2nm (N2) technology with gate-all-around transistors for 2025, positioning it at the industry's leading edge. SMIC, constrained by U.S. export controls that deny it access to EUV tools and advanced process equipment from key suppliers like ASML, Applied Materials, and Lam Research, faces immense challenges in advancing beyond its current plateau. The gap is therefore not merely a matter of calendar time but a structural divide enforced by geopolitical trade restrictions and a lack of access to the foundational tools required for next-generation semiconductor manufacturing.

The implications of this gap extend beyond simple process labels into economics, yield, and design enablement. TSMC's EUV-based processes offer superior transistor density, power efficiency, and performance, which are non-negotiable for leading-edge applications like premium smartphones, AI accelerators, and advanced computing. Its colossal scale and proven design infrastructure attract a global ecosystem of fabless companies, including Apple, NVIDIA, and AMD, creating a virtuous cycle of investment and innovation. In contrast, SMIC's 7nm process, while a significant domestic achievement, is understood to have significantly lower yield and higher production costs. This limits its viability to a select few domestic clients, primarily those with strategic national mandates, rather than commercially competitive global players. Furthermore, TSMC's roadmap includes advanced packaging technologies (like its 3D Fabric platform) that are critical for heterogeneous integration, a domain where SMIC's capabilities are still nascent. The divergence thus encapsulates the entire value chain, from basic manufacturing technology to the sophisticated co-design partnerships that define the cutting edge.

Looking forward, the trajectory of this gap through the latter half of the decade will be determined by two competing dynamics: the intensity of continued export controls and the efficacy of China's drive for semiconductor self-sufficiency. SMIC and its domestic equipment suppliers are the focal point of a massive national effort to build an indigenous supply chain. Progress is being made in areas like DUV lithography and process materials, but replicating the complexity and precision of EUV technology remains a multi-year, if not decade-long, challenge with no guarantee of success. Barring a major, unforeseen breakthrough in alternative lithography methods, SMIC will likely continue to refine its DUV-based nodes for improved yield and cost while falling further behind TSMC's accelerating pace. TSMC, meanwhile, continues to innovate with substantial R&D investments and is expanding its global manufacturing footprint to mitigate geopolitical risks. Consequently, the most probable scenario for 2025 and beyond is a persistent and likely widening gap in leading-edge logic manufacturing, with SMIC's role increasingly consolidated as the foundational supplier for China's mature and mid-tier node demands, while TSMC solidifies its position as the indispensable global foundry for the industry's most advanced technologies.